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(R)
74VHC174
HEX D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
s
s
s
s s
s
s
s
s s
HIGH SPEED: fMAX =175 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (Max.)
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74VHC174M 74VHC174T transfered to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The 74VHC174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. Information signals applied to D inputs are
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
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74VHC174
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 9 8 16 SYMBOL CLEAR Q0 to Q5 D0 to D5 CLOCK GND VCC NAME AND FUNCT ION Asyncronous Master Reset (Active LOW) Flip-Flop Outputs Data Inputs Clock Input (LOW-to-HIGH, Edge- Triggered) Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS CL EAR L H H H
X:Don't Care
OUT PUT S CLO CK X Q L L H Qn
F UNCTIO N CLEAR
D X L H X
NO CHANGE
LOGIC DIAGRAM
Thislogic diagram has notbe used to estimate propagation delays
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74VHC174
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V mA mA mA mA
o o
ICC or IGND DC VCC or Ground Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (see note 1) (VCC = 3.3 0.3V) (V CC = 5.0 0.5V) Parameter Valu e 2.0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 to 100 0 to 20 Unit V V V
o
C
ns/V ns/V
1) VIN from 30% to70%of VCC
DC SPECIFICATIONS
Symb ol Parameter T est Cond ition s V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 II ICC Input Leakage Current Quiescent Supply Current 0 to 5.5 5.5 IO=-50 A IO=-50 A IO=-50 A IO=-4 mA IO=-8 mA IO=50 A IO=50 A IO=50 A IO=4 mA IO=8 mA VI = 5.5V or GND VI = VCC or GND 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 4 2.0 3.0 4.5
o
Value T A = 25 C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 1.0 40 Typ . Max. -40 to 85 C Min . 1.5 0.7VCC 0.5 0.3VCC Max.
o
Un it
V V
V
V
A A
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AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
Symb ol Parameter V CC (V) tPLH tPHL Propagation Delay Time CK to Q Test Co ndition CL (pF ) 15 50 15 50 15 50 15 50 Value T A = 25 o C Min. Typ . Max. 7.2 11.0 9.7 4.9 6.4 7.4 9.9 5.1 6.6 14.5 7.2 9.2 11.4 14.9 7.6 9.6 5.0 5.0 5.0 5.0 5.0 4.5 0.0 0.5 3.0 2.5 15 50 15 50 95 55 130 90 150 85 175 120 80 50 110 80 MHz Un it -40 to 85 o C Min . Max. 1.0 13.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 16.5 8.5 10.5 13.5 17.0 9.0 11.0 5.0 5.0 5.0 5.0 6.0 4.5 0.0 0..5 3.0 2.5 ns ns ns ns ns ns
3.3(*) 3.3(*) 5.0(**) 5.0(**) 3.3(*) 3.3(*) 5.0 5.0(**)
(**)
tPHL
Propagation Delay Time CLR to Q
ns
tw tw ts th tREM fMAX
CLR pulse Width LOW CK pulse Width HIGH r LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Removal Time CLR to CK Maximum Clock Frequency
3.3 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 3.3 5.0(**) 5.0
(**) (*)
(*)
(*) Voltage range is 3.3V 0.3V (**) Voltage range is 5V 0.5V
CAPACITIVE CHARACTERISTICS
Symb ol Parameter T est Cond ition s
o
Value T A = 25 C Min. Typ . Max. -40 to 85 C Min . Max. 10
o
Un it
C IN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
4 29
10
pF pF
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/6 (per Flip-Flop)
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74VHC174
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter T est Cond ition s V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 -0.8 5.0 5.0 C L = 50 pF 3.5 1.5 Min. Typ . 0.3 -0.3 V Value T A = 25 o C Max. 0.8 -40 to 85 o C Min . Max. Un it
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
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74VHC174
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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74VHC174
WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
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74VHC174
Plastic DIP-16 (0.25) MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001C
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SO-16 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
P013H
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com .
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